The present invention pertains to an antisaturation circuit for PNP transistors in monolithic integrated circuits. Such integrated circuits are formed on a single chip of semiconductor, most of the times silicon, through a suitable sequence of fabrication phases comprising surface oxidation, photolithography, epitaxial growth, impurities diffusion, metallization. With these processes diodes, transistors and passive components are formed which are interconnected on the chip itself by means of suitable metallizations.
Integrated PNP transistors, that is formed on the substrate, that is on the chip of semiconductor material, present, in operation, a particular problem. When the PNP transistor is driven to the saturation zone of its characteristic, it may give rise to a leakage current toward the substrate which may result untolerable for the correct operation of the whole integrated circuit. Under saturation conditions, that is with the substantial dropping to zero of the V.sub.CE voltage of its transistor, the base may come to find itself at a lower potential with respect to the potential of the collector and thence the base-collector junction may become forward biased. This situation creates a parasitic PNP transistor through the base-collector junction of the real transistor whose collector functions as the emitter of the parasitic transistor the latter's collector being represented by the substrate of semiconductor material of the chip.
Naturally this problem is particularly felt in case of integrated PNP power transistors both for the levels of the currents as well as for the increased probability that such transistors be driven accidentally to saturation, for example, with the variation of the load impedance of the transistor.